MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH ANALOG DEVICES VISUALDSP PLUSPLUS Manual de usuario descargar pdf (Pagina 37)

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36 DSP Selection Guide

ADSP-TS101

Next Generation SHARC

®

DSP

Features

• 2 billion 16-bit MACs-per-second

• 550 MFLOP/watt – industry best

• 1.2 volt supply with 3.3 volt I/O

• 4.0 ns instruction cycle time at 250 MHz

• Eight 16-bit MACs/cycle with 40-bit

accumulation

• Two 32-bit MACs/cycle with 80-bit

accumulation

• 6 Mbit on-chip SRAM

• IEEE floating-point compatible

• 14 DMA channels

• 4 Link ports – 1 GByte/sec transfer rate, aggregate

• 32/64-bit external port – 800 MBytes/sec

• 128 general purpose registers

• Optimizing C/C++ compiler

• Glueless multiprocessing

• 19 x 19 mm or 27 x 27 mm PBGA

Benefits

• Flexible development environment

that supports both algebraic

assembly language and C/C++

• Large on-chip RAM makes

reprogramming easy

• 4 Link ports enable direct

chip-to-chip connections

without the need for complex

external circuitry

• VisualDSP++ tools support

provides same software interface

as other ADI DSPs

• Multiple-instruction, multiple-data

(MIMD) instructions

• Fully interruptible with full

computation performance

Applications

• Medical, CT, ultrasound

• Sonar systems

• Echo and noise cancellation systems

• Flight simulator

• Infrastructure equipment

• Military smart munitions

• Test equipment

• Imaging, printers, video

The ADSP-TS101 is the newest member of the

high performing SHARC

®

DSP family.

Operating at 250 MHz, TigerSHARC DSP

offers best-in-class floating-point performance

at a minimum power consumption. The

TigerSHARC DSP supports arithmetic for 8-,

16-, and 32-bit data, and contains 6 Mbit on-

chip SRAM internally organized in three banks

with user-defined partitioning. Three internal

128-bit wide internal buses provide a total

memory bandwidth of 8.64 Gbytes per second.

Development Tools

ADSP-TS101SKB1250X

ADSP-TS101SKB2250X

250

250

27 x 27 mm PBGA

19 x 19 mm PBGA

Model MHz Pkg

ADDS-TS101S-EZLITE

VDSP-TS-PC-FULL

VDSP-TS-PCFLOAT

ADDS-APEX-ICE

ADDS-SUMMIT-ICE

Evaluation Kit

VisualDSP++

VisualDSP++ Floating License

USB-Based Emulator

PCI-Based Emulator

K = Commercial Temp (-40ºC to +85ºC case)

IAB

PROGRAM SEQUENCER

PC BTB IRQ

ADDR

FETCH

INTEGER

J ALU

32 x32

32

INTEGER

K ALU

32 x32

DATA ADDRESS GENERATION

INPUT

FIFO

OUTPUT

BUFFER

OUTPUT

FIFO

CLUSTER

BUS

ARBITER

HOST

INTERFACE

MULTI-

PROCESSOR

INTERFACE

32

ADDRESS

CNTRL

64

DATA

INTERNAL MEMORY

MEMORY

M0

64 x 32

AD

MEMORY

M1

64 x 32

AD

MEMORY

M2

64 x 32

AD

PROCESSING ELEMENTS

DMA

CONTROLLER

32

DMA

DATA

CONTROL/

STATUS/

TCBs

DMA

ADDRESS

LINK PORT

CONTROLLER

CONTROL/

STATUS/

BUFFERS

LINK

DATA

L0

3

8

L1

3

8

L2

3

8

L3

3

8

I/O PROCESSOR LINK PORTS

X

REGISTER

FILE

32 x 32

MULTIPLIER

ALU

SHIFTER

DAB

128

128

Y

REGISTER

FILE

32 x 32

MULTIPLIER

ALU

SHIFTER

DAB

128

128

32

128

M0 ADDR

32

128

M1 DATA

32

128

M2 ADDR

M0 DATA

M1 ADDR

M2 DATA

32

I/O

ADDRESS

JTAG

PORT

6

SDRAM

CONTROLLER

EXTERNAL PORT

32

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 61 62

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