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MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH ANALOG DEVICES VISUALDSP PLUSPLUS Manual de usuario Pagina 25

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24 DSP Selection Guide
SHARC
®
DSP Family Benchmarks
Just looking at the cycle time, clock speed,
MIPS or MFLOPS of a DSP cannot give an
accurate indication of the true performance of
the processor. Benchmarks are important in that
they show how a particular DSP performs in
the context of an application. The smaller the
benchmark number, the quicker the algorithm
execution. If a DSP can perform the task quick-
er, the processor can perform more tasks in a
given amount of time.
SHARC DSPs are the highest performance
32-bit DSPs available. These processors excel
at IEEE floating-point math, 32-bit fixed-point
math, and extended precision 40-bit floating-
point math.
The ADI 32-bit DSP family offers a maximum
performance for minimum system cost, while
dramatically shortening product development
time and critical time-to-market.
TMS320C6701
TMS320C6711
TMS320C6712
ADSP-21065L
ADSP-21160N
ADSP-21161N
DSP
Processor
167 MHz
150 MHz
100 MHz
66 MHz
95 MHz
100 MHz
Instruction
Rate
Instruction
Cycle Time
19, 875
19, 875
19, 875
18, 221
10,778*
10,778*
Number
of Cycles
0.12 ms
0.13 ms
0.19 ms
0.27 ms
0.10 ms
0.09 ms
Total FFT
Time
6 ns
6.7 ns
10 ns
15 ns
11 ns
10 ns
1024-Point Complex FFT (in place)
32-BIT Floating-Point DSPs
Clock Speed
Instruction Cycle Time
MFLOPS Sustained, Peak
MOPS (32-bit Fixed-Point)
Sustained, Peak
1024-Point Complex FFT
(Radix 4, with Digit Reverse)
FIR Filter (per Tap)
IIR Filter (per Biquad)
Matrix Multiply
(3x3) x (3x1)
(4x4) x (4x1)
Divide (y/x)
Inverse Square Root
66 MHz
15 ns
132, 198 MFLOPS
132, 198 MFLOPS
0.27 ms (SISD)
100 MHz
10 ns
400, 600 MFLOPS
400, 600 MFLOPS
0.09 ms*
15 ns
60 ns
135 ns
240 ns
90 ns
135 ns
5 ns*
20 ns*
45 ns*
80 ns*
60 ns*
90 ns*
Specification Source: TI, website www.ti.com
* These benchmarks provide single channel extrapolation of measured dual channel processing performance.
http://www.analog.com/dsp
ADSP-21065LBenchmarks ADSP-21161N
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