MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH ANALOG DEVICES VISUALDSP PLUSPLUS Manual de usuario descargar pdf (Pagina 36)

DSP Selection Guide 35

SHARC

DSP Family

Real-Time, Multiprocessing Leader

The Analog Devices SHARC

DSP family fea-

tures a "super" Harvard architecture optimized

to enable a variety of real-time embedded

applications. These 32-bit DSPs allow users to

program with equal efficiency in both fixed-

point and floating-point arithmetic. The unique

memory architecture – two large on-chip, dual-

ported SRAM blocks coupled with the sophisti-

cated I/O processor – gives the SHARC DSPs

the bandwidth for sustained high-speed compu-

tations for real-time embedded DSP develop-

ment.

Code-compatibility helps to keep development

time at a minimum, and maximize our cus-

tomers' software investments.

The original Single-Instruction, Single-Data

(SISD) SHARC DSPs feature a broad range of

memory sizes and price points. For very high

performance applications, ADI has extended

the architecture to a code-compatible, Single-

Instruction, Multiple-Data (SIMD) platform.

The next generation TigerSHARC 128-bit DSP

combines multiple computation units for float-

ing-point and fixed-point processing, as well as

very wide word widths, by using a Multiple-

Instruction, Multiple Data (MIMD) platform.

Its ultra-high-performance static superscaler

architecture is optimized for computationally

demanding and multiprocessor applications.

SHARC DSPs are the leader in multiprocessing

applications. Patented link port technology has

helped establish SHARC as a de facto standard.

Applications

• Prosumer audio

• 3D graphics

• Arcade games

• Imaging

• Video conferencing

• Medical imaging

• Radar and sonar guidance

• Audio equipment

• Call processing

• Speech recognition

• Cellular base stations

• Instrumentation

Market Focused

Multiprocessor

Low Cost

SHARC

1200 MFLOPs

From $5

Price performance

Market focused

SHARC

Tiger

SHARC

250-500 MHz

6 Mbits

New MP support

Higher performance

New peripherals

Target at vertical markets

ADSP-2106x

120-198 MFLOPS

.5-4 Mbits memory

ADSP-21161

ADSP-21160

600 MFLOPS

1 Mbit

570 MFLOPS

4 Mbits

Integrated MP

Time/Process

MFLOPS

32-BIT

Generic Package

S, CA

B,S

Max MIPS

100

250

Vcc

1.9/3.3V

2.5/3.3V

1.8/3.3V

3.3V

3.3/5V

1.2/3.3V

On-Chip

SRAM

Serial

Ports

Price*

(1000)

$145.00

$24.63

$19.50

$100.00

$37.43

$249.29

$207.00

ADSP-21160N

ADSP-21160M

ADSP-21161N

ADSP-21065L

ADSP-21062/L

ADSP-21061/L

ADSP-21060/L

ADSP-TS101S

B = Plastic Ball Grid Array (PBGA)

G = Ceramic Pin Grid Array (PGA)

S = Plastic Quad Flat Pack (PQFP)

CA = Mini Ball Grid Array (MBGA)

Package:

US Dollars. Lowest grade suggested resale price per unit in 1000 unit quantities

All pricing is budgetary - subject to change

SHARC Roadmap

Commitment to Code Compatibility into Tomorrow

544

Mbits

Mbit

Kbits

Mbits

Mbit

Mbits

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 61 62

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MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH ANALOG DEVICES VISUALDSP PLUSPLUS Manual de usuario Pagina 36

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