MATLAB SIMULINK HDL CODER 1 Manual de usuario Pagina 44

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9/21/2011
44
Use Model-Based Design to provide
an integrated workflow
Things to remember ….
DESIGN
Speed up algorithm development
with a unified design environment
Automate manual steps in
FPGA implementation to enable
shorter iteration c
y
cles
Algorithm
Development
MATLAB
Simulink
Stateflow
94
y
Integrate FPGA development tools to
reduce verification time
Shorter implementation time by 48% (total project 33%)
Reduced FPGA prototype development schedule by 47%
ROI: Customer Adoption Of Model-Based Design
Time spent on FPGA/ASIC implementation
Shorter design iteration cycle by 80%
1
st
FPGA Prototype 2
nd
FPGA Prototype
1
st
FPGA Prototype
95
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