MATLAB SIMULINK VERIFICATION AND VALIDATION - S Guía de usuario Pagina 485

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Top-Level Model Coverage Report
19-45
Simulink Design Verifier Coverage
If you select Simulink Design Verifier, the analysis collects coverage data for all
Simulink Design Verifier blocks in your model.
For an example of how this works, open the sldvdemo_debounce_testobjblks model.
This model contains two Test Objective blocks:
The True block defines a property that the signal have a value of 2.
The Edge block, inside the Masked Objective subsystem, describes the property where
the output of the AND block in the Masked Objective subsystem changes from 2 to 1.
The Simulink Design Verifier software analyzes this model and produces a harness
model that contains test cases that achieve certain test objectives. To see if the original
model achieves those objectives, simulate the harness model and collect model coverage
data. The model coverage tool analyzes any decision points or values within an interval
that you specify in the Test Objective block.
In this example, the coverage report shows that you achieved 100% coverage of the True
block because the signal value was 2 at least once. The signal value was 2 in 6 out of 14
time steps.
The input signal to the Edge block achieved a value of True once out of 14 time steps.
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